1. Field of the Invention
The present invention relates to an electronic apparatus applicable to an image capture apparatus such as a digital camera, a digital video camera, or a portable telephone equipped with a camera.
2. Related Background Art
Conventionally, a CPU or a direct memory access (DMA) controller (referred to as DMAC, hereinafter) operates as a bus master to control a bus in many cases. Typically, the CPU operates as a bus master to occupy the bus. If the DMAC operates as a bus master, the DMAC transmits a bus request to the CPU. The CPU releases the bus upon reception of the bus request. Then, a bus use privilege (referred to as bus privilege, hereinafter) is transferred to the DMAC. As a result, the DMAC operates as a bus master. Conventionally, such the system has generally been employed to set the DMAC as a bus master (e.g., see Japanese Patent Application Laid-Open No. H05-334232).
However, when employing the above-mentioned system, unless the bus master transfers a bus privilege, another bus master cannot obtain the bus privilege, and the bus master that cannot obtain the bus privilege is set into a locked state. Thus, the above system is called an interlock system.
A recent progress in a multifunctional configuration of a system has been accompanied with connection of many bus masters to the system in addition to the CPU and the DMAC. Then, the other bus masters are locked during a period that a certain bus master occupies a bus. Thus, according to the above-mentioned system, the other bus masters must wait for access to the bus. In other words, a waiting time until the other bus masters can use the bus becomes longer.
To eliminate the waiting time until the bus can be used, a split bus transaction system has been generally employed. According to this split bus transaction system, an address phase and a data phase are separated from each other, and a plurality of bus masters reserve use of addresses for a slave device to be accessed in the address phase. Then, the plurality of bus masters access data of the slave device in asynchronously generated data phase.
By employing the split transaction system, it becomes possible to prevent a locked state of the bus master as much as possible without occupying the bus by a certain bus master. Accordingly, total bus efficiency (band width) can be increased more in the case of the split bus transaction system than that in the case of the interlock system.
However, in the split bus transaction system, for example, requests made from the plurality of bus masters to a synchronous dynamic random access memory (SDRAM) which is a bus slave are mixed in the address phase. Thus, the split bus transaction system is advantageous in that the bus privileges can be uniformly provided to the plurality of bus masters (locked state of a particular bus master is prevented). However, performance of the SDRAM is greatly reduced depending on the accessed state of the plurality of bus master, which is a problem.
Under those circumstances, the inventors of the present invention have conducted thorough studies on causes of a reduction in the performance of the SDRAM in case that the plurality of bus masters reserve addresses for the slave device in the address phase. The causes of the reduction in performance of the SDRAM will be described below.
(1) Case where Reading (Read) and Writing (Write) Alternately Occur in Access to SDRAM
FIGS. 7A to 7D are timing charts each showing an example of operation timing in an SDRAM of a double data rate (DDR) type. The SDRAM of the DDR type can process data at both of leading and trailing edges of a clock signal. When a comparison is made with an SDRAM of a single data rate (SDR) type that performs processing data at one of leading edge and trailing edge of a clock signal, the data can be processed at a speed twice faster.
FIGS. 7A to 7D are timing charts when a burst length is set to 8 (BL=8) and column address strobe latency (CAS latency) is set to 2 (CL=2).
The timing charts of FIGS. 7A to 7D each show a case where an access is made to the same row address, and no precharging occurs. Depending on the access order, a timing gap may be generated during a time period from a current access to the next access.
As shown in FIG. 7A, the timing gap is not generated when the Read command occurs subsequently to the Read command. As shown in FIG. 7B, the timing gap is not generated when the Write command occurs subsequently to the Write command.
Contrary to this, as shown in FIG. 7C, the timing gap is 1 cycle when the Write command is issued subsequently to the Read command. As shown in FIG. 7D, the timing gap is 3.5 cycles when the Read command is issued subsequently to the Write command.
From the foregoing, it can be understood that the performance of the SDRAM becomes higher with less timing gap in the case of performing continuous access to the reading (Read) and the writing (Write).
(2) Case where Bank Conflict Occurs Upon Access to SDRAM
FIGS. 8A to 8D are timing charts each showing an example of operation timing in an SDRAM of a DDR type which needs precharging. FIGS. 8A to 8D also show the time charts, as in the case of FIGS. 7A to 7D, a bust length is set to 8 (BL=8) and CAS latency is set to 2 (CL=2).
According to the split bus transaction system, the plurality of bus masters access the SDRAM which is a bus slave. Owing to this, as shown in FIGS. 8A to 8D, there is a possibility in that access to different pages (row addresses) of the same bank (referred to as bank conflict, hereinafter) will increase. When such the access occurs, page closing (precharge to SDRAM) and page opening (active to SDRAM) become necessary. As a result, there may be possibility that a timing gap in bank conflict will greatly reduce transfer efficiency of the bus.
As shown in FIG. 8A, the timing gap is 6 cycles when a Read command, a Pre Charge command, an active (ACT) command, and a Read command are issued in this order. As shown in FIG. 8B, the timing gap is 8 cycles when the Write command, the Pre Charge command, the ACT command, and the Write command are issued in this order.
As shown in FIG. 8C, the timing gap is 4.5 cycles when the Read command, the Pre Charge command, the ACT command, and the Write command are issued in this order. As shown in FIG. 8D, the timing gap is 9.5 cycles when the Write command, the Pre Charge command, the ACT command, and the Read command are issued in this order.
Such the timing gap varies slightly depending on the types of the DRAM. Regarding the access to the SDRAM which needs precharging (Pre Charge), however, many timing gaps are typically necessary, and those timing gaps reduce the performance of the SDRAM.
In particular, in the SDRAM of the DDR type, the reduction in performance caused by the timing gap is conspicuous. If the burst length is set to 8 and the access the SDRAM of the DDR type is performed, the number of clock cycles necessary for one burst transfer is 4. Presuming that the continuous transfer of the reading (Read) or the writing (Write) where no bank conflict occurs is carried out, a band of substantially 100% can be obtained as a band width of the SDRAM.
However, if a timing gap of 1 cycle is generated during one burst transfer, the total number of clock cycles becomes 5 including 4-cycle access and the timing gap of 1 cycle. Hence, the band width is reduced by 20% (according to the timing gap ratio).
If the burst length is set to 8 and the access to the SDRAM of the SDR type is performed, the number of clock cycles necessary for one burst transfer is 8. Accordingly, the total number of the clock cycles becomes 9 when the timing gap of 1 cycle occurs, and the band width is reduced by about 11% (according to a timing gap ratio).
As described above, the data is accessed at a clock rate twice faster in the case of the SDRAM of the DDR type than that in the case of the SDRAM of the SDR type. However, nothing is different from the SDRAM of the SDR type in a command issuance period other than a data access period, and a period of the timing gap generation. Accordingly, expecting that a double band corresponding to the clock rate of the SDRAM of the DDR type is the highest performance band, a band loss of 1 cycle will be felt twice, i.e., the band loss of 2 cycles. Thus, a timing gap generated during access to the SDRAM is greatly affected by the performance of the SDRAM even in the case of 1 cycle.
Therefore, when an operation of high real timeness is intended to be secured, there has been a problem in that the reduction occurs in performance of the bus slave.